The present invention relates to a data transfer system having a storage device such as a disk having a buffer capable of transferring data at higher speed than the storage device and a controller with a cache memory, and also relates to a data transfer method for such a system.
In a storage device system having a controller with a cache memory, a difference between data transfer speeds of the storage device and controller can be alleviated by a processor access to data in the cache memory pre-loaded from the storage device. It is important to make a probability of presence of processor accessing data in the cache memory, or a hit percentage, as large as possible in order to efficiently use the cache memory. To this end, not only the data requested by the processor but also the data expected to be read in future are transferred to the cache memory. As described in CMG'90 PROCEEDINGS (1990), pp. 27 to 37, in a sequential read, the controller operates to load not only the track to be accessed but also the following three tracks. It can be expected therefore that all the following accesses become a hit. Also in an access other than the sequential access, the accessed record as well as some records in its track are loaded in the cache memory. It can be expected therefore to improve the hit percentage in an access other than the sequential access.
A technique regarding a buffered storage device is disclosed in JP-A-62-3455. With this technique, the provision of a buffer memory to each storage device eliminates a wait time of the disk to be caused by the contention of a data transfer path between storage devices.
Another technique is also disclosed in JP-A-62-92022 for a storage device system having storage devices and a plurality of controllers each having a cache memory. With this technique, assuming that the ratio of the data transfer speed from a storage device to a controller to that from a controller to a processor is 1:n (1.ltoreq.n), the data transfer to the channel starts when (1-1/n) times all the data to be transferred to the channel is loaded from the storage device to the controller is completed, the amount of all the data being calculated from a LOCATE instruction issued from the processor. The data transferred from the storage device to the cache memory of the controller includes the requested data and pre-loaded data. Such data transfer requires still further consideration.
A disk unit having a buffer memory is described in U.S. Pat. No. 5,187,778 under the title of "Buffered Disk Unit and Method of Transferring Data Therein". However, this system has no cache memory.